coreboot/src/security
Keith Short 7006458777 post_code: add post code for failure to load next stage
Add a new post code, POST_INVALID_ROM, used when coreboot fails to
locate or validate a resource that is stored in ROM.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-22 14:21:57 +00:00
..
tpm vboot: include vb2_sha.h when required 2019-05-09 06:32:44 +00:00
vboot post_code: add post code for failure to load next stage 2019-05-22 14:21:57 +00:00
Kconfig security/tpm: Move tpm TSS and TSPI layer to security section 2018-01-18 01:35:31 +00:00
Makefile.inc security/tpm: Move tpm TSS and TSPI layer to security section 2018-01-18 01:35:31 +00:00