2910a2b545
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/* chips are arbitrary chips (superio, southbridge, etc.)
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* They have private structures that define chip resources and default
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* settings. They have four externally visible functions for control.
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* They have a generic component which applies to all chips for
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* path, etc.
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*/
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/* some of the types of resources chips can control */
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#ifndef CONFIG_CHIP_CONFIGURE
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#define CONFIGURE(dev, pass) chip_configure(chip, pass)
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#else
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#define CONFIGURE(dev, pass)
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#endif
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struct com_ports {
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unsigned int enable,baud, base, irq;
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};
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/* lpt port description.
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* Note that for many chips you only really need to define the
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* enable.
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*/
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struct lpt_ports {
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unsigned int enable, // 1 if this port is enabled
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mode, // pp mode
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base, // IO base of the parallel port
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irq; // irq
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};
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enum chip_pass {
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CONF_PASS_PRE_CONSOLE,
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CONF_PASS_PRE_PCI,
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CONF_PASS_PRE_DEVICE_ENUMERATE,
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CONF_PASS_PRE_DEVICE_CONFIGURE,
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CONF_PASS_PRE_DEVICE_ENABLE,
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CONF_PASS_PRE_DEVICE_INITIALIZE,
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CONF_PASS_PRE_BOOT
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};
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/* linkages from devices of a type (e.g. superio devices)
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* to the actual physical PCI device. This type is used in an array of
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* structs built by NLBConfig.py. We owe this idea to Plan 9.
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*/
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struct chip;
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/* there is one of these for each TYPE of chip */
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struct chip_control {
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void (*enable)(struct chip *, enum chip_pass);
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char *path; /* the default path. Can be overridden
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* by commands in config
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*/
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// This is the print name for debugging
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char *name;
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};
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struct chip {
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struct chip_control *control; /* for this device */
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char *path; /* can be 0, in which case the default is taken */
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char *configuration; /* can be 0. */
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int irq;
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struct chip *next, *children;
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/* there is one of these for each INSTANCE of a chip */
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void *chip_info; /* the dreaded "void *" */
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};
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extern struct chip root;
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extern void chip_configure(struct chip *, enum chip_pass);
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