coreboot/src
Furquan Shaikh 28e61f1634 device: Use __pci_0_00_0_config in config_of_soc()
This change updates the definition of config_of_soc() to a macro that
expands to __pci_0_00_0_config instead of accessing the config
structure by referencing the struct device. This allows linker to
optimize out unused portions of the device tree from early stages.

With this change, bootblock .text section size drops as follows:

Platform       | Size without change | Size with change | Reduction   |
---------------|---------------------|------------------|-------------|
GLK (ampton)   |  27112 bytes        |  9832 bytes      | 17280 bytes |
APL (reef)     |  26488 bytes        | 17528 bytes      |  8960 bytes |
TGL (volteer2) |  47760 bytes        | 21648 bytes      | 26112 bytes |
CML (hatch)    |  40616 bytes        | 22792 bytes      | 17824 bytes |
JSL (waddledee)|  37872 bytes        | 19408 bytes      | 18464 bytes |
KBL (soraka)   |  31840 bytes        | 21568 bytes      | 10272 bytes |

As static.h is now included in device.h which gets pulled in during
the unit tests, a dummy static.h is added under tests/include.

Change-Id: I1fbf5b9817065e967e46188739978a1cc96c2c7e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-12 05:22:40 +00:00
..
acpi acpi,soc/intel/common: add support for Intel Low Power Idle Table 2021-01-11 20:49:23 +00:00
arch arch/x86/Makefile.inc: Clean up generated assembly stubs 2021-01-08 08:10:04 +00:00
commonlib drivers/tpm: Implement full PPI 2020-12-21 02:38:20 +00:00
console lib/trace: Remove TRACE support 2020-12-02 23:35:58 +00:00
cpu cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot 2021-01-11 23:42:55 +00:00
device device: Add new Kconfig VGA_ROM_RUN_DEFAULT for mainboard user 2021-01-10 17:50:29 +00:00
drivers drivers/genesyslogic/gl9763e: Add HS400ES compatibility settings 2021-01-12 04:52:16 +00:00
ec ec/google/chromeec: add SSFC CBI support 2021-01-08 08:25:42 +00:00
include device: Use __pci_0_00_0_config in config_of_soc() 2021-01-12 05:22:40 +00:00
lib arch/x86: Move prologue to .init section 2021-01-07 11:02:03 +00:00
mainboard mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN value 2021-01-12 03:00:41 +00:00
northbridge nb/intel/gm45: Guard macro parameters 2021-01-10 23:03:33 +00:00
security */Makefile.inc: Add some INTERMEDIATE targets to .PHONY 2021-01-08 08:08:07 +00:00
soc soc/intel/alderlake: Add PCH ID 0x5182 2021-01-12 05:18:51 +00:00
southbridge sb/intel/bd82x6x: Use PCH_LPC_DEV macro 2021-01-10 15:42:05 +00:00
superio src/superio: trim and move Makefile.inc, instead use wildcard matches 2020-12-27 14:46:07 +00:00
vendorcode {soc,vc,mb}/intel: Drop support for Cannon Lake SoC 2021-01-11 17:23:53 +00:00
Kconfig Kconfig: Show console debug options if loglevel override is set 2020-12-11 15:58:24 +00:00