coreboot/src
Kyösti Mälkki 28837c6b01 allwinner/a10: Hide SoC specific UART functions
If platform has a component coreboot has to communicate with using
one of the UARTs, that device would not be part of the SoC and
must not use functions specific to a10 UART.

Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5469
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:37 +02:00
..
arch uart: Support multiple ports 2014-04-30 06:59:05 +02:00
console uart: Support multiple ports 2014-04-30 06:59:05 +02:00
cpu allwinner/a10: Hide SoC specific UART functions 2014-04-30 06:59:37 +02:00
device OxPCIe uart: Split PCI bridge control 2014-04-09 11:29:45 +02:00
drivers uart: Support multiple ports 2014-04-30 06:59:05 +02:00
ec ec/compal/ene932: Update to use coreboot EC-mainboard API 2014-04-19 03:49:48 +02:00
include uart: Support multiple ports 2014-04-30 06:59:05 +02:00
lib Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
mainboard uart: Support multiple ports 2014-04-30 06:59:05 +02:00
northbridge Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
soc console: Move newline translation outside console_tx_byte 2014-04-09 13:21:25 +02:00
southbridge AGESA SPI: Fix Kconfig options 2014-04-29 17:31:40 +02:00
superio superio/winbond/w83627ehg: Convert romstage to generic component 2014-04-28 20:14:58 +02:00
vendorcode vendorcode/amd/agesa/fam14: Build as a static library 2014-04-15 17:23:37 +02:00
Kconfig Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00