Ronald G. Minnich df78385663 1. Add call to stage 1 ht setup for mainboard ... 2. add support for same, brought over from v2. Still no luck on 8111 ISA however. What are we missing? The symptom is simple: Device 0:b.0 does not appear in the PCI list, so device with vid/did 1022/7468 is not there, so we can not enable 5 MiB flash addressing. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@824 f3766cd6-281f-0410-b1cd-43a5c92072e9		2008-08-26 22:12:02 +00:00
..
adl	Change v3 makefile rules to be source-based, part I.	2008-08-18 11:15:43 +00:00
amd	1. Add call to stage 1 ht setup for mainboard	2008-08-26 22:12:02 +00:00
artecgroup	Change v3 makefile rules to be source-based, part I.	2008-08-18 11:15:43 +00:00
emulation	Fix Kconfig dependencies and update defconfigs.	2008-08-18 16:48:27 +00:00
gigabyte	This now compiles and has a simple error on build to stage2.	2008-08-23 16:51:00 +00:00
pcengines	Fix Kconfig dependencies and update defconfigs.	2008-08-18 16:48:27 +00:00
Kconfig	The m57sli almost builds. It's pretty empty. The dtc is not run .	2008-08-01 17:03:22 +00:00