coreboot/src
Alexandru Gagniuc 27bb6ad046 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
Only the WLAN control pin and the lid switch input are declared, as
those are the only pins whose function is known and tested.

Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5463
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12 21:16:19 +02:00
..
arch console: Refactor uart8250/NE2K 2014-04-09 13:28:33 +02:00
console console: Remove old fix for DEBUG_SMI 2014-04-09 13:26:48 +02:00
cpu agesa: Always include family* Kconfig 2014-04-12 13:34:36 +02:00
device OxPCIe uart: Split PCI bridge control 2014-04-09 11:29:45 +02:00
drivers OxPCIe uart: Move under drivers/uart 2014-04-09 11:30:53 +02:00
ec ec/compal/ene932/acpi: Let mainboard define the ACPI lid object 2014-04-12 20:26:04 +02:00
include console: Refactor uart8250/NE2K 2014-04-09 13:28:33 +02:00
lib uart: Redefine Kconfig options 2014-04-09 11:24:43 +02:00
mainboard hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI 2014-04-12 21:16:19 +02:00
northbridge console: Move newline translation outside console_tx_byte 2014-04-09 13:21:25 +02:00
soc console: Move newline translation outside console_tx_byte 2014-04-09 13:21:25 +02:00
southbridge intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03 2014-04-11 15:21:03 +02:00
superio uart: Redefine Kconfig options 2014-04-09 11:24:43 +02:00
vendorcode Add the Rangeley FSP include & srx directories 2014-04-11 17:29:40 +02:00
Kconfig SeaBIOS: have coreboot pass the choice to run optionroms in parallel 2014-04-07 11:54:26 +02:00