coreboot/src/soc
Werner Zeh 279afdc24b intel/apollolake: Add parameter to enable VTD in devicetree
The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.

Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.

Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05 06:34:44 +00:00
..
amd soc/amd/stoneyridge: Reboot if missing MRC cache info 2019-02-04 21:17:57 +00:00
cavium cbmem_top: Fix comment and remove upper limit 2019-01-24 13:54:21 +00:00
imgtec (console,drivers/uart)/Kconfig: Fix dependencies 2018-11-21 22:49:48 +00:00
intel intel/apollolake: Add parameter to enable VTD in devicetree 2019-02-05 06:34:44 +00:00
mediatek google/kukui: Move some initialization from bootblock to verstage 2019-01-29 13:10:47 +00:00
nvidia console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
qualcomm console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
rockchip src: Don't use a #defines like Kconfig symbols 2019-01-28 13:41:28 +00:00
samsung src: Don't use a #defines like Kconfig symbols 2019-01-28 13:41:28 +00:00
sifive riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00
ucb riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00