coreboot/src/include/device
Tan, Lean Sheng 26136092c0 soc/intel/common: Add Elkhartlake Device IDs
Add Elkhartlake CPU, SA and PCH IDs.
EHL PCH is code named as MCC.
Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22 15:42:26 +00:00
..
dram
azalia.h
azalia_device.h
cardbus.h
device.h
drm_dp_helper.h
hypertransport.h
hypertransport_def.h
i2c.h
i2c_bus.h
i2c_simple.h
mmio.h
path.h
pci.h
pci_def.h
pci_ehci.h
pci_ids.h soc/intel/common: Add Elkhartlake Device IDs 2020-01-22 15:42:26 +00:00
pci_mmio_cfg.h
pci_ops.h
pci_rom.h
pci_type.h
pciexp.h
pcix.h
pnp.h
pnp_def.h
pnp_ops.h
pnp_type.h
resource.h
smbus.h
smbus_def.h
smbus_host.h sb/intel/common: Declare common smbus_base() and enable_smbus() 2020-01-14 18:18:26 +00:00
spi.h