Kangheui Won 260f0f93ef cezanne/psp_verstage: add reset/timer svc ... The new cezanne PSP release added support for these svcs. So add those functionality back to cezanne psp_verstage. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-06-07 05:16:20 +00:00
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cezanne	cezanne/psp_verstage: add reset/timer svc	2021-06-07 05:16:20 +00:00
common	cezanne/psp_verstage: add reset/timer svc	2021-06-07 05:16:20 +00:00
picasso	soc/amd/picasso: remove warm reset flag code	2021-06-02 15:27:26 +00:00
stoneyridge	soc/amd: factor out ACPI ALIB function numbers to common code	2021-05-08 17:56:10 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00