Saurabh Mishra 254a4b9072 soc/intel/lunarlake: Support stepping A0_2 ... Details: - Add support for new Lunar Lake MCH ID 0x6410 - Add new CPU id 0xb06d1 Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage. Below prints verified on Lunar Lake RVP board (lnlrvp). [DEBUG] MCH: device id 6410 (rev 02) is LunarLake M Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>		2024-05-12 18:57:39 +00:00
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amd	include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNT	2023-07-18 21:51:33 +00:00
intel	soc/intel/lunarlake: Support stepping A0_2	2024-05-12 18:57:39 +00:00
power	src/cpu/power9: move part of scom.h to scom.c	2023-04-18 13:05:56 +00:00
x86	smmstorev2: Load the communication buffer at SMM setup	2024-04-05 07:10:17 +00:00
cpu.h	x86: Separate CPU and SoC physical address size	2023-12-22 12:26:59 +00:00