coreboot/src
Aaron Durbin 2524be4aff fsp1_1: pass ROM_SIZE to FSP for cacheable RO region
As vboot verification works on regions outside of CBFS
pass the entire ROM_SIZE to FSP for creating a cacheable
RO region.

Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't
work with non-power of 2 CBFS_SIZE. In practice the entire
ROM should be attempted to be cached.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados w/ a 3MiB CBFS_SIZE.

Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c
Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309770
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12260
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:40:05 +01:00
..
acpi tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
arch ACPI: Add functions for DMAR I/O-APIC and HPET entries 2015-11-04 16:17:12 +01:00
commonlib cbmem: add coreboot table records for each cbmem entry 2015-11-03 00:19:46 +01:00
console tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
cpu cpu/microcode: Remove EXTERNAL / ADDED_DURING_BUILD variables 2015-11-05 02:24:45 +01:00
device tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
drivers fsp1_1: pass ROM_SIZE to FSP for cacheable RO region 2015-11-05 17:40:05 +01:00
ec tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
include drivers/pc80: Rework normal / fallback selector code 2015-11-03 21:55:20 +01:00
lib drivers/pc80: Rework normal / fallback selector code 2015-11-03 21:55:20 +01:00
mainboard mainboard: Remove last_boot NVRAM option 2015-11-05 02:21:52 +01:00
northbridge nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge 2015-11-05 16:09:42 +01:00
soc skylake: Set Pkg Power clamping bit in Power Limit MSR 2015-11-05 17:39:46 +01:00
southbridge sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETs 2015-11-04 18:17:11 +01:00
superio Drop SuperIO smsc/fdc37m60x 2015-11-04 01:00:19 +01:00
vendorcode tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
Kconfig drivers/pc80: Rework normal / fallback selector code 2015-11-03 21:55:20 +01:00