coreboot/src
Sridhar Siricilla 248dbe0908 soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
The patch enables cse_fw_sync() before DRAM initialization.
cse_fw_sync() sends HECI commands in order to set CSE's boot partition
and to trigger CSE firmware update.
As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI
command. Since CSE supports the command after DRAM Initialization,
cse_fw_sync() is called after DRAM initialization.

Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command
before DRAM initialization too. So, cse_fw_sync() is called before DRAM
initialization.

BUG=b:175516533
TEST=Dependency with CSE Litev16.0.15.1545 integration

Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-29 09:46:01 +00:00
..
acpi dptf: Add support for one more temperature sensor 2021-11-26 11:19:32 +00:00
arch arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax 2021-11-25 10:42:17 +00:00
commonlib commonlib/cbmem_id.h: Add names for some IDs 2021-11-25 11:13:41 +00:00
console src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
cpu cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI 2021-11-29 09:45:14 +00:00
device device/pci_device.c: Scan only one device for PCIe 2021-11-29 03:19:51 +00:00
drivers drivers/smmstore: Remove SMMSTORE_IN_CBFS 2021-11-27 19:23:14 +00:00
ec ec/google/chromeec: Support 5 temperature sensors 2021-11-26 11:19:52 +00:00
include pci_mmio_cfg: Rename pcicfg to pci_map_bus 2021-11-29 03:20:54 +00:00
lib cbfs: Add helper functions to look up size and type of a file 2021-11-17 12:46:25 +00:00
mainboard lippert/frontrunner-af: Use common cimx/sb800 ASL 2021-11-28 16:40:03 +00:00
northbridge nb/intel/sandybridge: Add support for DPR 2021-11-26 11:25:19 +00:00
security security/intel/txt: Fix GETSEC checks in romstage 2021-11-27 14:20:16 +00:00
soc soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init 2021-11-29 09:46:01 +00:00
southbridge lippert/frontrunner-af: Use common cimx/sb800 ASL 2021-11-28 16:40:03 +00:00
superio superio/smsc/sch5545: Disable PS/2 lines isolation during init 2021-11-27 14:23:08 +00:00
vendorcode vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 2021-11-15 09:57:35 +00:00
Kconfig Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set 2021-11-13 00:20:11 +00:00