coreboot/src/soc/intel
Aaron Durbin 245f7561d4 UPSTREAM: soc/intel/common: log event when MRC cache is updated
Log when the MRC cache is attempted to be updated with status
of success or failure. Just one slot is supported currently
which is deemed 'normal'. This is because there are more slots
anticipated in the future.

BUG=chrome-os-partner:59395
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17231
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)

Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da
Reviewed-on: https://chromium-review.googlesource.com/408264
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07 11:02:59 -08:00
..
apollolake UPSTREAM: soc/intel/apollolake: Implement SPI flash status register read 2016-11-04 04:54:11 -07:00
baytrail UPSTREAM: lib/prog_loaders: use common ramstage_cache_invalid() 2016-11-03 14:44:12 -07:00
braswell UPSTREAM: Makefile.inc: Use $(MAINBOARDDIR) 2016-09-07 00:16:17 -07:00
broadwell UPSTREAM: lib/prog_loaders: use common ramstage_cache_invalid() 2016-11-03 14:44:12 -07:00
common UPSTREAM: soc/intel/common: log event when MRC cache is updated 2016-11-07 11:02:59 -08:00
fsp_baytrail UPSTREAM: fsp_baytrail: Refactor code for SPI debug messages 2016-09-07 11:31:46 -07:00
fsp_broadwell_de UPSTREAM: soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled 2016-10-11 14:32:15 -07:00
quark UPSTREAM: soc/intel/quark: Fix FSP 2.0 build 2016-09-30 18:03:30 -07:00
sch UPSTREAM: src/soc: Remove unnecessary whitespace before "\n" and "\t" 2016-09-02 07:11:51 -07:00
skylake UPSTREAM: intel/{skylake,apollolake}: Enable signalling of error condition 2016-11-04 04:53:19 -07:00