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coreboot/src/include/console
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Keith Short 24302633a5 post_code: add post code for memory error 
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22 16:54:46 +00:00
..
cbmem_console.h coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
console.h console: Add new function die_with_post_code() 2019-05-20 14:44:27 +00:00
flash.h coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
ne2k.h coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
post_codes.h post_code: add post code for memory error 2019-05-22 16:54:46 +00:00
qemu_debugcon.h console/qemu_debugcon: Support additional stages 2019-03-23 07:05:28 +00:00
spi.h coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
spkmodem.h coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
streams.h console: Add write line routine 2016-08-10 22:30:19 +02:00
uart.h coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
usb.h coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
vtxprintf.h src/include: Add space after comma 2017-03-09 17:19:16 +01:00