coreboot/src/mainboard/intel/leafhill
Subrata Banik 2715cdb3f3 soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.

TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.

Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:50:03 +00:00
..
acpi_tables.c
board_info.txt
bootblock.c
brd_gpio.h
devicetree.cb soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array 2018-03-16 04:43:01 +00:00
dsdt.asl soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi 2019-11-01 11:50:03 +00:00
Kconfig soc,mb/intel: clean up remaining FSP2.0 socs/boards 2019-10-26 15:47:49 +00:00
Kconfig.name
leafhill.8192.fmd
leafhill.16384.fmd
mainboard.c
Makefile.inc
romstage.c