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Felix Held 230dbd6d3c soc/amd/cezanne: add empty ramstage FCH support 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-29 22:57:01 +00:00
..
acpi ACPI: Do minor improvements on GNVS 2021-01-29 10:21:25 +00:00
arch stage_cache: Add resume_from_stage_cache() 2021-01-29 10:53:33 +00:00
commonlib
console
cpu cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE 2021-01-28 12:34:52 +00:00
device device/Kconfig: Declare MMCONF symbols' type once 2021-01-29 17:46:55 +00:00
drivers stage_cache: Add resume_from_stage_cache() 2021-01-29 10:53:33 +00:00
ec
include stage_cache: Add resume_from_stage_cache() 2021-01-29 10:53:33 +00:00
lib stage_cache: Add resume_from_stage_cache() 2021-01-29 10:53:33 +00:00
mainboard mb/emulation/qemu-q35: Consolidate host bridge definitions 2021-01-29 18:36:22 +00:00
northbridge device/Kconfig: Declare MMCONF symbols' type once 2021-01-29 17:46:55 +00:00
security
soc soc/amd/cezanne: add empty ramstage FCH support 2021-01-29 22:57:01 +00:00
southbridge soc/intel: Drop CMEM from GNVS 2021-01-29 16:25:25 +00:00
superio superio/nuvoton/common/Kconfig: Remove HWM config 2021-01-29 09:39:43 +00:00
vendorcode vc/google/chromeos/Kconfig: Remove unused NO_TPM_RESUME 2021-01-29 09:40:19 +00:00
Kconfig