coreboot/src/soc
Duncan Laurie 22f1dcdfc4 baytrail: Update to microcode 31E and fix C-state table
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.

BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi, check that C1/C2/C3 are all used now

Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178461
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4984
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:05:29 +02:00
..
intel baytrail: Update to microcode 31E and fix C-state table 2014-05-08 07:05:29 +02:00
Kconfig Move ARCH_* from board/Kconfig to cpu or soc Kconfig. 2014-05-03 00:25:20 +02:00
Makefile.inc baytrail: add initial support 2014-01-31 16:36:59 +01:00