coreboot/src/soc/intel
Aaron Durbin 22ea007891 fsp1_1: fsp_relocate: use struct region_device and struct prog
Using struct prog and struct region_device allows for the
caller to be none-the-wiser about where FSP gets placed. It
also allows for the source location to be abstracted away
such that it doesn't require a large mapping up front to
do the relocation. Lastly, it allows for simplifying the
intel/commmon FSP support in that it can pass around a
struct prog.

BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.

Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30
Original-Signed-off-by: Aaron Durbin <adurbin@chroumium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290830
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c
Signed-off-by: Aaron Durbin <adurbin@chroumium.org>
Reviewed-on: http://review.coreboot.org/11193
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:18:13 +02:00
..
baytrail x86: Drop -Wa,--divide 2015-07-07 18:30:55 +02:00
braswell intel/braswell: fix build 2015-07-29 19:26:34 +02:00
broadwell azalia: fix up and clean up shrinkage of boilerplate code 2015-07-14 13:40:07 +02:00
common fsp1_1: fsp_relocate: use struct region_device and struct prog 2015-08-14 15:18:13 +02:00
fsp_baytrail intel/fsp_baytrail: Support Baytrail FSP Gold4 release 2015-07-21 22:32:23 +02:00
skylake Skylake: Add ASL code to enable GPIO controller 2015-08-14 15:17:53 +02:00