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coreboot/src/soc
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Tristan Shieh 223434644a mediatek: Refactor USB code among similar SoCs 
Refactor USB code which will be reused among similar SoCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: I06fefb4149a489be991e13ddf624082d11e31765
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-17 12:05:25 +00:00
..
amd soc/amd/stoneyridge: Define PM USB Enable register 2018-10-14 19:11:54 +00:00
broadcom soc/broadcom/cygnus: Increase romstage SRAM size in memlayout 2018-08-13 12:16:32 +00:00
cavium soc/cavium/cn81xx: Drop dead do_soft_reset() implementation 2018-10-17 12:02:35 +00:00
imgtec src: Use tabs for indentation 2018-10-08 09:46:16 +00:00
intel drivers/intel/fsp2_0: Hook up IntelFSP repo 2018-10-12 23:20:53 +00:00
lowrisc/lowrisc mb/lowrisc: Remove the Nexys4DDR port 2018-09-26 15:36:40 +00:00
mediatek mediatek: Refactor USB code among similar SoCs 2018-10-17 12:05:25 +00:00
nvidia tegra124_lp0: make sure to build with compiler.h included 2018-10-11 11:00:49 +00:00
qualcomm Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
rockchip drivers/i2c: Add i2c TPM support for different stages 2018-08-10 23:25:52 +00:00
samsung Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
sifive soc/sifive/fu540: Document #if ENV_ROMSTAGE line 2018-09-26 18:52:54 +00:00
ucb arch/riscv: provide a monotonic timer 2018-09-14 09:28:06 +00:00