Xiang Wang 21ed107958 riscv: add entry assembly file for RAMSTAGE ... RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-09-05 10:04:57 +00:00
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arch	riscv: add entry assembly file for RAMSTAGE	2018-09-05 10:04:57 +00:00
bits.h
mcall.h	riscv: add include/arch/smp/ directory	2018-07-12 11:53:30 +00:00
stdint.h	riscv: update the definition of intptr_t/uintptr_t	2018-08-30 14:48:26 +00:00
vm.h	riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page	2018-09-04 12:35:29 +00:00