Felix Held 4a88b03a6c soc/amd/cezanne/chipset.cb: clean up and change some aliases ... With the aliases some of the comments are redundant. I'm still not sure if the Ethernet controller on the embedded SKUs supports 10G or only 1G. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e432c12f92a622f8ee05be19acb2c304dd74afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>		2021-03-04 23:51:39 +00:00
..
acpi	soc/amd/cezanne/acpi: Add globalnvs.asl	2021-02-25 23:41:53 +00:00
include/soc	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
acpi.c	soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settings	2021-02-26 23:45:22 +00:00
aoac.c
bootblock.c
chip.c
chip.h
chipset.cb	soc/amd/cezanne/chipset.cb: clean up and change some aliases	2021-03-04 23:51:39 +00:00
config.c
cpu.c
data_fabric.c
early_fch.c	soc/amd/cezanne: Disable legacy DMA IO ports	2021-03-02 22:17:20 +00:00
fch.c
fsp_params.c
fw.cfg	soc/amd/cezanne: Add PSP whitelist debug unlock support	2021-03-01 08:27:57 +00:00
gpio.c
Kconfig	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
Makefile.inc	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
pcie_gpp.c
reset.c
romstage.c	soc/amd/cezanne: Disable legacy DMA IO ports	2021-03-02 22:17:20 +00:00
root_complex.c
smihandler.c	soc/amd/cezanne/smihandler: implement S3 entry SMI handler	2021-03-04 19:55:56 +00:00
smu.c	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
uart.c