coreboot/src/northbridge/intel
Damien Zammit a090ae04c2 nb/intel/x4x: Add DMI/EP init
The values were obtained from vendor bios at runtime.
I am not 100% sure of the sequence required to initiate them,
but guessed from the gm45 code.  There may be some status bytes
needed to be polled during the sequence that is missing,
but as I don't have bios writer's datasheet it's very hard
for me to know.

Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14925
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 20:02:09 +02:00
..
common northbridge/intel: move mrccache.c of sandybridge + haswell to common 2016-03-11 19:00:14 +01:00
e7501 northbridge/intel: add missing #include guards 2016-02-28 18:55:32 +01:00
e7505 northbridge/intel: add missing #include guards 2016-02-28 18:55:32 +01:00
fsp_rangeley header files: Fix guard name comments to match guard names 2016-01-18 04:07:53 +01:00
fsp_sandybridge northbridge/intel: move mrc_cache definition into a common header 2016-03-11 18:56:21 +01:00
gm45 nb/intel/gm45: Fix native text mode initialization 2016-05-04 19:57:03 +02:00
haswell northbridge/intel: move mrccache.c of sandybridge + haswell to common 2016-03-11 19:00:14 +01:00
i440bx northbridge/intel/i440bx: Unify UDELAY selection 2016-03-10 16:55:35 +01:00
i855 northbridge/intel: add missing #include guards 2016-02-28 18:55:32 +01:00
i945 northbridge/i945/gma: Re-enable NVRAM tft_brightness 2016-03-11 00:48:54 +01:00
i3100 cpu/x86/mtrr: move cache_ramstage() to its only user 2016-03-16 18:55:51 +01:00
i5000 tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
i82810 northbridge/intel/i82810: Unify UDELAY selection 2016-03-13 00:46:55 +01:00
i82830 northbridge/intel/i82830: Unify UDELAY selection 2016-03-12 22:03:42 +01:00
nehalem northbridge/intel: move mrccache.c of sandybridge + haswell to common 2016-03-11 19:00:14 +01:00
pineview intel/pineview: Don't try to store 34 bits in 32 2016-05-08 21:36:32 +02:00
sandybridge Fix leaking CONFIG_VGA=y 2016-05-31 17:18:59 +02:00
x4x nb/intel/x4x: Add DMI/EP init 2016-05-31 20:02:09 +02:00