Jianjun Wang 2183484e7a mb/google/cherry: Pre-initialize PCIe at the bootblock stage ... Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and waiting for 100ms, which is currently the only function of 'mtk_pcie_pre_init', so that the extra 100ms delay in ramstage is avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>		2022-03-29 15:41:43 +00:00
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acpi	coreboot_tables.c: Expose the ACPI RSDP	2022-03-09 14:21:01 +00:00
arch	prog_loader: Change legacy_romstage_select_and_load() to return cb_err	2022-03-09 17:20:48 +00:00
commonlib	commonlib/bsd: Add struct name "mem_chip_channel" for external access	2022-03-18 15:40:26 +00:00
console	console: Fix LOG_FAST macro	2022-02-22 23:13:50 +00:00
cpu	cpu/x86/smm: Add weak SoC init and exit methods	2022-03-10 17:06:51 +00:00
device	device/pciexp_device: Set resources for pciexp_hotplug_dummy_ops	2022-03-28 02:28:52 +00:00
drivers	src: Remove unused <bootmode.h>	2022-03-27 15:31:07 +00:00
ec	ec/starlabs/merlin: Don't store EC values on change	2022-03-21 16:57:54 +00:00
include	include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values	2022-03-28 14:14:27 +00:00
lib	lib/device_tree.c: zero-initialize new DT nodes	2022-03-22 20:45:26 +00:00
mainboard	mb/google/cherry: Pre-initialize PCIe at the bootblock stage	2022-03-29 15:41:43 +00:00
northbridge	nb/intel/sandybridge/acpi: Support setting PCI bars above 4G	2022-03-28 15:28:19 +00:00
security	{drivers/security}: Replace cb_err_t with enum cb_err	2022-03-09 08:40:43 +00:00
soc	mb/google/cherry: Pre-initialize PCIe at the bootblock stage	2022-03-29 15:41:43 +00:00
southbridge	sb/amd/hudson/spi.c: Use C over CPP conditional	2022-03-25 20:06:57 +00:00
superio	Use the fallthrough statement in switch loops	2022-02-16 21:29:53 +00:00
vendorcode	vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table	2022-03-27 15:16:17 +00:00
Kconfig	src/Kconfig: Update the path to 'c_start.S' for GDB_STUB config	2022-02-22 20:49:10 +00:00