erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
coreboot/src/cpu/intel/common
History
Jeremy Compostella 1eff77bc59 arch/x86: Reduce max phys address size for Intel TME capable SoCs 
On Intel SoCs, if TME is supported, TME key ID bits are reserved and
should be subtracted from the maximum physical addresses available.

BUG=288978352
TEST=Verified that DMAR ACPI table `Host Address Width` field on rex
     went from 45 to 41.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-12 08:12:02 +00:00
..
acpi
common.h cpu/intel: Move is_tme_supported() from soc/intel to cpu/intel 2023-09-12 08:11:17 +00:00
common_init.c arch/x86: Reduce max phys address size for Intel TME capable SoCs 2023-09-12 08:12:02 +00:00
fsb.c cpu: Include <cpu/cpu.h> instead of <arch/cpu.h> 2022-11-08 14:38:28 +00:00
hyperthreading.c cpu: Include <cpu/cpu.h> instead of <arch/cpu.h> 2022-11-08 14:38:28 +00:00
Kconfig cpu/intel/common: Fill cpu voltage in SMBIOS tables 2020-11-22 22:31:40 +00:00
Makefile.inc arch/x86: Reduce max phys address size for Intel TME capable SoCs 2023-09-12 08:12:02 +00:00
voltage.c cpu/intel/common: Fill cpu voltage in SMBIOS tables 2020-11-22 22:31:40 +00:00