Philipp Hug 1ed082bc8b riscv: simplify timer interrupt handling ... Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. TEST=Run linux on sifive unleashed Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/29340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2018-10-30 02:09:05 +00:00
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acpi
arch	riscv: simplify timer interrupt handling	2018-10-30 02:09:05 +00:00
commonlib	src: Remove unneeded whitespace	2018-10-23 15:52:09 +00:00
console
cpu	x86/mp_init: Add configurable stack size for SMM relocate	2018-10-29 18:01:43 +00:00
device	src: Remove unneeded whitespace	2018-10-23 15:52:09 +00:00
drivers	src/drivers/pc80/tpm/tis.c: Dont use port value when invalid.	2018-10-29 14:27:16 +00:00
ec	ec/google/chromeec: Use common MEC interface	2018-10-18 15:01:40 +00:00
include	selfboot: create selfboot_check function, remove check param	2018-10-25 16:57:51 +00:00
lib	Add selfboot to the romstage	2018-10-30 00:37:04 +00:00
mainboard	mb/google/poppy/variants/nami: Add field to identify single channel DDR	2018-10-29 16:49:43 +00:00
northbridge	nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware	2018-10-24 10:04:41 +00:00
security	vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic	2018-10-24 09:07:43 +00:00
soc	sifive/fu540: correct cbmem support	2018-10-30 02:07:12 +00:00
southbridge	sb/amd: Use 'unsigned int' to bare use of 'unsigned'	2018-10-24 10:01:55 +00:00
superio	src: Remove unneeded whitespace	2018-10-23 15:52:09 +00:00
vendorcode	vendorcode/intel/fsp/icelake: Add icelake FSP header file template	2018-10-26 11:21:05 +00:00
Kconfig