a2977ae72d
Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSP-M: SkipCpuReplacementCheck PCH HSIO Tuning UPDs FSP-S: PcieRpHotPlug TccActivationOffset TccOffsetClamp TccOffsetLock TccOffsetTimeWindowForRatl USB3 HSIO Tuning UPDs BUG=none BRANCH=none TEST=build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib40d226dd2ecc4fb34965e1f2c416c53edef01d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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