Lee Leahy 1d14b3e926 soc/intel: Add Skylake SOC support ... Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2015-07-16 17:24:48 +02:00
..
baytrail	x86: Drop -Wa,--divide	2015-07-07 18:30:55 +02:00
braswell	Braswell: Use CBFS image type name	2015-07-14 20:28:13 +02:00
broadwell	azalia: fix up and clean up shrinkage of boilerplate code	2015-07-14 13:40:07 +02:00
common	soc/intel/common: Restrict common romstage/ramstage code to FSP	2015-06-26 00:01:57 +02:00
fsp_baytrail	Move baytrail & fsp_baytrail to the common IFD interface.	2015-07-02 02:21:33 +02:00
skylake	soc/intel: Add Skylake SOC support	2015-07-16 17:24:48 +02:00