Tim Van Patten 1cf0acdc1c soc/amd/mendocino: Add low/no battery VRM limit registers ... Add DPTC Low/No battery VRM limit registers to throttle the SOC. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-09-19 09:56:06 +00:00
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amd	soc/amd/mendocino: Add low/no battery VRM limit registers	2022-09-19 09:56:06 +00:00
cavium	soc/cavium,ti: Do resource transition	2022-06-29 11:55:01 +00:00
example/min86	src/mb: Add SPDX identifiers to files missing them	2022-08-11 17:52:19 +00:00
intel	soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID	2022-09-16 16:17:36 +00:00
mediatek	soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)"	2022-09-14 12:49:44 +00:00
nvidia	timer: Change timer util functions to 64-bit	2022-09-14 11:55:39 +00:00
qualcomm	sc7180: Fix DDR training failure during warm reset with OTA	2022-09-13 13:05:46 +00:00
rockchip	soc/(amd|rockchip): Update vb2ex_hwcrypto implementations to new API req	2022-08-12 20:59:59 +00:00
samsung	timer: Change timer util functions to 64-bit	2022-09-14 11:55:39 +00:00
sifive/fu540	src/soc: Get rid of most src/soc/Kconfig files	2022-06-24 03:59:36 +00:00
ti	soc/cavium,ti: Do resource transition	2022-06-29 11:55:01 +00:00
ucb/riscv	src/soc: Get rid of most src/soc/Kconfig files	2022-06-24 03:59:36 +00:00