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coreboot/src/northbridge
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Dave Frodin b738913ce0 northbridge/intel/fsp_rangeley: Correct MMIO size setting 
The Rangeley chipset has the MMIO PCI config space feature
enabled at 0xe0000000-0xefffffff. This is a 256MB space
which covers all of config space. The ACPI table for
this space only defines it as being 64MB. This change
fixes that setting.

Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/10047
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-05-01 17:29:00 +02:00
..
amd kbuild: automatically include northbridges 2015-04-29 18:12:14 +02:00
dmp/vortex86ex kbuild: automatically include northbridges 2015-04-29 18:12:14 +02:00
intel northbridge/intel/fsp_rangeley: Correct MMIO size setting 2015-05-01 17:29:00 +02:00
rdc/r8610 kbuild: automatically include northbridges 2015-04-29 18:12:14 +02:00
via kbuild: automatically include northbridges 2015-04-29 18:12:14 +02:00