coreboot/src
Duncan Laurie 1a50d08fc7 glados: Add Board ID support
Add support for reading board id and populating it in the
coreboot tables so it is exposed to payloads.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=boot on glados and look for reported board ID

Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004
Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297746
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10 09:50:35 +00:00
..
acpi
arch x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE 2015-09-09 19:36:08 +00:00
console
cpu linking: add and use LDFLAGS_common 2015-09-09 19:35:54 +00:00
device symbols: add '_' to pci_drivers and cpu_drivers symbols 2015-09-05 15:36:23 +00:00
drivers FSP: Pass FSP image base address to find_fsp 2015-09-10 09:43:13 +00:00
ec chromeec: Add kconfig entry for EC PD support 2015-09-09 20:23:04 +00:00
include rmodule: use program.ld for linking 2015-09-09 19:35:30 +00:00
lib x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE 2015-09-09 19:36:08 +00:00
mainboard glados: Add Board ID support 2015-09-10 09:50:35 +00:00
northbridge x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
soc skylake: Enable DPTF based on devicetree setting 2015-09-10 09:47:57 +00:00
southbridge x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
superio
vendorcode verstage: use common program.ld for linking 2015-09-09 19:35:20 +00:00
Kconfig Kconfig: Remove EXPERT mode 2015-08-30 07:50:47 +00:00