coreboot/src/soc
Angel Pons 192b57cc8b amd/{hudson,stoney,picasso}: Drop PM2 settings from FADT
The PM2_CNT register block is no longer needed, as explained in some
comments. While they may have been copy-pasted around a lot, they are at
least true for Hudson, and it makes sense to assume that they are true
for newer chipsets as well. As per the ACPI specification, version 6.3,
section 4.8.1.3 (PM2 Control Register):

 This register block is optional, if not supported its block pointer and
 length contain a value of zero.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.

Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:16:46 +00:00
..
amd amd/{hudson,stoney,picasso}: Drop PM2 settings from FADT 2020-07-20 13:16:46 +00:00
cavium src: Remove unused 'include <types.h>' 2020-07-14 16:10:17 +00:00
intel src: Drop useless PM1b settings from FADT 2020-07-20 13:16:05 +00:00
mediatek src: Remove unused 'include <stdint.h> 2020-07-14 16:11:10 +00:00
nvidia src: Remove unused 'include <stdint.h> 2020-07-14 16:11:10 +00:00
qualcomm src: Remove unused 'include <stdint.h> 2020-07-14 16:11:10 +00:00
rockchip soc/rockchip/rk3399/display.c: Add missing include 2020-07-14 16:11:42 +00:00
samsung soc/samsung/exynos5420: Drop dead code 2020-07-09 21:37:01 +00:00
sifive treewide: Add Kconfig variable MEMLAYOUT_LD_FILE 2020-06-13 06:49:23 +00:00
ucb soc/ucb/riscv: Add chip_operations stub 2020-05-28 09:30:35 +00:00