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coreboot/src/cpu/amd
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Xavi Drudis Ferran 19245c94c8 Improving BKDG implementation of P-states, 
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Factor out some common expressions.
Add an error message when coreboots hangs waiting for a pstate
that never comes (it happened to me), and throw some
paranoia at it for good mesure.

If I understood BKDG fam10 CPUs never need a software initiated vid transition,
because the hardware knows what to do when you just request
a Pstate change if the cpu is properly configured. In fact
unifying a little what PVI and SVI do was better for my board (SVI).
So I drop transitionVid, which I didn't understand either (why
did it have a case for PVI if it is never called for PVI ?
Why did the PVI case distinguigh cpu or nb when PVI is
theoretically single voltage plane ? ).

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:02:40 +00:00
..
agesa_wrapper Add AMD cpu wrapper code. Patch 4 of 8. 2011-02-14 18:42:12 +00:00
car According to AMD documentation, cache type WP should be used for 2011-02-10 20:49:56 +00:00
dualcore Eliminate SET_NB_CFG_54 option. There was no board that 2010-11-18 00:11:32 +00:00
microcode Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
model_10xxx Improving BKDG implementation of P-states, 2011-02-28 03:02:40 +00:00
model_fxx It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. 2011-02-26 13:34:01 +00:00
model_gx1 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
model_gx2 Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code 2010-12-30 19:23:29 +00:00
model_lx Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
mtrr MTRR related improvements for AMD family 10h and family 0Fh systems 2010-11-13 19:07:59 +00:00
quadcore Eliminate SET_NB_CFG_54 option. There was no board that 2010-11-18 00:11:32 +00:00
sc520 We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it. 2010-10-12 17:34:08 +00:00
smm SMM on AMD K8 Part 2/2 2010-12-18 23:30:59 +00:00
socket_754 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_939 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_940 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_AM2 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_AM2r2 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_AM3 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_ASB2 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_F SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_F_1207 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
socket_S1G1 SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
Kconfig Add AMD cpu wrapper code. Patch 4 of 8. 2011-02-14 18:42:12 +00:00
Makefile.inc Add AMD cpu wrapper code. Patch 4 of 8. 2011-02-14 18:42:12 +00:00