0b87bb7726
Some GPIO pins are shared with PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, simply setting 0:14.4 disabled in the devicetree does not work here yet. Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8495 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) |
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