V Sowmya 187f06f07e soc/intel/common: Add Kconfig for CSE RW firmware version ... This patch adds a kconfig SOC_INTEL_CSE_RW_VERSION to pass the CSE RW firmware version from the mainboard. This will be extracted by makefile to update the cse_rw_metadata structure. Right now the required tool to extract the CSE RW version from the blob is still under development and after the official version of the tool is released, version will be extracted by parsing the CSE RW blob. BUG=b:169077783 Cq-Depend: chrome-internal:3402224, chrome-internal:3397863, chromium:2473603, chromium:2473603, chromium:2535950 Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47430 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-11-18 01:26:08 +00:00
..
acpi	soc/intel/common/acpi: correct indentation	2020-10-19 06:59:48 +00:00
basecode	soc/intel/common: Keep common non-IP code block inside basecode	2020-09-21 16:16:46 +00:00
block	soc/intel/common: Add Kconfig for CSE RW firmware version	2020-11-18 01:26:08 +00:00
pch	src/soc/intel: Drop unneeded empty lines	2020-09-21 16:15:25 +00:00
acpi.h
acpi_wake_source.c
fsp_reset.c	soc/intel/common: Create common Intel FSP reset code block	2020-11-02 10:43:40 +00:00
hda_verb.c
hda_verb.h
Kconfig.common	soc/intel: Configure PAVP at compile-time	2020-10-12 23:11:04 +00:00
Makefile.inc	soc/intel/common: Create common Intel FSP reset code block	2020-11-02 10:43:40 +00:00
mma.c
mma.h
nhlt.c
reset.c	Revert "soc/intel: Refactor do_global_reset() function"	2020-09-22 05:13:39 +00:00
reset.h	Revert "soc/intel: Refactor do_global_reset() function"	2020-09-22 05:13:39 +00:00
smbios.c
smbios.h
tpm_tis.c
vbt.c
vbt.h