coreboot/src/cpu/amd/pi
Kyösti Mälkki 187543c90d AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.

In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.

Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01 05:50:52 +01:00
..
00630F01 AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT 2016-12-01 05:50:52 +01:00
00660F01 AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT 2016-12-01 05:50:52 +01:00
00670F00 AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT 2016-12-01 05:50:52 +01:00
00730F01 AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT 2016-12-01 05:50:52 +01:00
amd_late_init.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
cache_as_ram.inc AGESA binaryPI: Fix cache-as-ram for x86_64 2016-11-25 10:32:07 +01:00
heapmanager.c src/cpu: Remove whitespace after sizeof 2016-10-04 14:32:38 +02:00
Kconfig ACPI S3: Remove HIGH_MEMORY_SAVE where possible 2016-11-09 20:52:07 +01:00
Makefile.inc cpu/amd: Update files for 00670F00 2016-11-02 18:35:20 +01:00
s3_resume.c AMD binaryPI: Delay ACPI S3 backup until ramstage loader 2016-11-09 20:53:03 +01:00
s3_resume.h AMD binaryPI: Split romstage ram stack 2016-07-15 12:20:21 +02:00
spi.c spi: Clean up SPI flash driver interface 2016-11-22 17:32:09 +01:00