coreboot/src/soc/intel
Lee Leahy 16cc414df9 UPSTREAM: soc/intel/quark: Disable FSP serial output
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8
(BIOS_SPEW).  Use the console log level to choose between the serial
port address and NULL and pass it to FSP for the serial port address.

TEST=Build and run on Galileo Gen2.

BUG=None
BRANCH=None

Change-Id: I26b61715ba158389727dd332e20fe6c80bf23784
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/368404
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-12 05:24:13 -07:00
..
apollolake UPSTREAM: soc/apollolake: Return correct wake status in _SWS 2016-08-11 20:39:54 -07:00
baytrail UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
braswell UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
broadwell UPSTREAM: intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano 2016-08-07 21:43:48 -07:00
common UPSTREAM: soc/intel/common: Fix build error in reset.c 2016-08-05 11:45:22 -07:00
fsp_baytrail UPSTREAM: Remove non-ascii & unprintable characters 2016-08-05 11:45:20 -07:00
fsp_broadwell_de UPSTREAM: fsp_broadwell_de: Add DMAR table to ACPI 2016-08-10 20:06:53 -07:00
quark UPSTREAM: soc/intel/quark: Disable FSP serial output 2016-08-12 05:24:13 -07:00
sch UPSTREAM: intel/sch: Merge northbridge and southbridge in src/soc 2016-05-20 17:08:20 -07:00
skylake UPSTREAM: soc/intel/skylake: Correct address of I2C5 Device 2016-08-11 20:39:47 -07:00