Jonathan Zhang 15fc45982b soc/intel/xeon_sp/spr: Add header files and romstage code ... Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>		2023-03-19 09:49:03 +00:00
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amd	soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h	2023-03-08 20:15:09 +00:00
intel	soc/intel/xeon_sp/spr: Add header files and romstage code	2023-03-19 09:49:03 +00:00
power	include: Add SPDX-License-Identifiers to files missing them	2022-08-01 13:59:11 +00:00
x86	cpu/x86/cache: CLFLUSH programs to memory before running	2023-03-13 13:42:32 +00:00
cpu.h	cpu/cpu.h: Change the function signature	2022-12-10 17:54:53 +00:00