coreboot/src/soc
Francois Toguo 15cbc3b599 soc/intel/tigerlake: Add CrashLog implementation for intel TGL
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.

BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-22 07:22:50 +00:00
..
amd ACPI: Use common OperationRegion for PCI_MMCONF 2021-02-20 21:38:54 +00:00
cavium cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
example arch/x86: Move prologue to .init section 2021-01-07 11:02:03 +00:00
intel soc/intel/tigerlake: Add CrashLog implementation for intel TGL 2021-02-22 07:22:50 +00:00
mediatek memlayout: Store region sizes as separate symbols 2021-02-19 08:39:26 +00:00
nvidia src: Remove useless comments in "includes" lines 2021-02-04 10:18:49 +00:00
qualcomm memlayout: Store region sizes as separate symbols 2021-02-19 08:39:26 +00:00
rockchip soc/rockchip/rk3399/sdram: Remove superfluous parameter 2021-02-22 07:21:48 +00:00
samsung src: Remove unused <boot_device.h> 2021-02-10 07:22:08 +00:00
sifive memlayout: Store region sizes as separate symbols 2021-02-19 08:39:26 +00:00
ti soc/ti/am335x/header.c: Add missing include 2021-02-03 08:55:15 +00:00
ucb