Kyösti Mälkki e522258907 AGESA f14: Fix memory clock register decoding ... Bottom five LSBs are used to store the running frequency of memory clock. Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19042 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>		2017-04-08 15:19:09 +02:00
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amd	AGESA f14: Fix memory clock register decoding	2017-04-08 15:19:09 +02:00
google	vboot: Move remaining features out of vendorcode/google/chromeos	2017-03-28 22:18:13 +02:00
intel	KBL: Update FSP headers - upgrade to FSP 2.0.0	2017-04-07 21:59:53 +02:00
siemens	vendorcode/siemens: Ensure a given info block is available for a field	2016-12-06 09:59:11 +01:00
Makefile.inc	vendorcode/siemens: Add hwilib for Siemens specific info struct	2016-04-28 08:15:47 +02:00