coreboot/src/soc
Michael Niewöhner 14512f9a9b soc/intel/common/block/gpio: add code for NMI enabling
Especially server boards, like the Supermicro X11SSM-F, often have a NMI
button and NMI functionality that can be triggered via IPMI. The purpose
of this is to cause the OS to create a system crashdump from a hang
system or for debugging.

Add code for enabling NMI interrupts on GPIOs configured with
PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI
function was copied and adapted. The `pad_community` struct gained two
variables for the registers.

Also register the NMI for LINT1 in the MADT in accordance to ACPI spec.

Test: Linux detects the NMI correctly in dmesg:
[    0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:10:24 +00:00
..
amd src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
cavium cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
example x86: Add a minimal example SoC along with a board 2020-10-30 21:34:18 +00:00
intel soc/intel/common/block/gpio: add code for NMI enabling 2020-12-04 00:10:24 +00:00
mediatek cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
nvidia cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
qualcomm cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
rockchip cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
samsung cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
sifive cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ti cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ucb