ba757a71fe
The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
26 lines
683 B
C
26 lines
683 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CPU_CPU_H
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#define CPU_CPU_H
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#include <arch/cpu.h> /* IWYU pragma: export */
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#include <stdint.h>
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void cpu_initialize(void);
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uintptr_t cpu_get_lapic_addr(void);
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struct bus;
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unsigned int cpu_phys_address_size(void);
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unsigned int soc_phys_address_size(void);
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#if ENV_RAMSTAGE
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#define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver")))
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#else
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#define __cpu_driver __attribute__((unused))
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#endif
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/** start of compile time generated pci driver array */
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extern struct cpu_driver _cpu_drivers[];
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/** end of compile time generated pci driver array */
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extern struct cpu_driver _ecpu_drivers[];
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#endif /* CPU_CPU_H */
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