Huayang Duan 131f3435fc soc/mediatek/mt8192: Do memory pll init before calibration ... Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode. TEST=Confirm Memory PLL frequency is right by frequency meter Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>		2020-12-22 03:00:07 +00:00
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amd	soc/amd/picasso: move sb_clk_output_48Mhz from acp to fch	2020-12-19 16:29:44 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/xeon_sp: Use common block ACPI	2020-12-22 02:59:18 +00:00
mediatek	soc/mediatek/mt8192: Do memory pll init before calibration	2020-12-22 03:00:07 +00:00
nvidia	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
qualcomm	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
rockchip	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
samsung	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
sifive	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ti	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
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