coreboot/src
Kyösti Mälkki 12cd397ae5 UPSTREAM: intel/i82801dx: Support 2MiB FWH part
Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2477affed9f5d910ce657a809962356193eeb85f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0288d676
Original-Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17918
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/427469
2017-01-13 15:22:00 -08:00
..
acpi
arch
commonlib
console
cpu
device
drivers
ec
include
lib
mainboard
northbridge
soc
southbridge UPSTREAM: intel/i82801dx: Support 2MiB FWH part 2017-01-13 15:22:00 -08:00
superio
vboot
vendorcode
Kconfig