Alexey Buyanov 12016969c5 soc/intel/tigerlake: Rename pch_init() code ... Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>		2020-08-26 07:36:21 +00:00
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amd	soc/amd/picasso: If psp_verstage is in RO, don't reset on error	2020-08-25 16:23:26 +00:00
cavium	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
intel	soc/intel/tigerlake: Rename pch_init() code	2020-08-26 07:36:21 +00:00
mediatek	soc/mediatek/mt8192: Add dramc param struct	2020-08-25 13:48:15 +00:00
nvidia	src: Remove unused 'include <stddef.h>	2020-08-18 12:15:44 +00:00
qualcomm	src: Remove unused 'include <delay.h>'	2020-08-18 12:19:18 +00:00
rockchip	src/soc/rockchip: Add missing <{stddef,stdint}.h>	2020-07-29 09:37:22 +00:00
samsung	src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h>	2020-07-29 09:34:55 +00:00
sifive	soc/sifive: Drop unneeded empty lines	2020-08-24 09:16:48 +00:00
ti	cpu/ti/am335x: Move from cpu to soc in tree	2020-08-19 07:17:37 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00