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Puthikorn Voravootivat 111f9a9bcd mb/google/poppy/variants/atlas: Remove B0D4 _PSV 
Per Intel, the internal thermal protection is working better
than putting B0D4 _PSV in dptf.

BUG=b:131251533
TEST=Get ~10% better Octane score.
Correct TCC and TCC offset in MSR register.

Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-15 17:48:01 +00:00
..
acpi
arch Remove unnecessary ENV_RAMSTAGE guard 2019-05-14 06:56:59 +00:00
commonlib vboot: include vb2_sha.h when required 2019-05-09 06:32:44 +00:00
console Remove unnecessary ENV_RAMSTAGE guard 2019-05-14 06:56:59 +00:00
cpu lapic/lapic_cpu_init: Add cpu_add_map_entry() to store default_apic_id 2019-05-13 02:07:09 +00:00
device device: ignore NONE devices behind bridge 2019-05-07 16:05:27 +00:00
drivers Remove unnecessary ENV_RAMSTAGE guard 2019-05-14 06:56:59 +00:00
ec src/ec/lenovo/h8/acpi: Serialize Control Method 2019-05-13 09:26:58 +00:00
include boot_device: Constify argument 2019-05-12 07:47:45 +00:00
lib Remove unnecessary ENV_RAMSTAGE guard 2019-05-14 06:56:59 +00:00
mainboard mb/google/poppy/variants/atlas: Remove B0D4 _PSV 2019-05-15 17:48:01 +00:00
northbridge nb/intel/sandybridge: Move boot_count_increment() 2019-05-13 09:29:33 +00:00
security vboot: Turn vboot_logic_executed() into a static inline 2019-05-10 21:43:15 +00:00
soc soc/intel/cannonlake: Support different SPD read type for each slot 2019-05-15 17:47:13 +00:00
southbridge i82801gx/bootblock: Use macro instead of magic number 2019-05-13 09:31:28 +00:00
superio superio/ite: Add IT8786E-I 2019-05-15 17:45:41 +00:00
vendorcode vendorcode/google/chromeos: Use explicit zero check in ACPI code 2019-05-09 15:34:53 +00:00
Kconfig Kconfig: Create RAMPAYLOAD kconfig 2019-05-12 03:10:24 +00:00