coreboot/src
Michał Żygowski 1119428693 soc/intel/braswell/smbus: Enable early SMBus in romstage
Enable early SMBus support compatible with SPD library using Intel SB
common SMBus API.

TEST=boot Protectli FW2B with new FSP, MemoryInit should pass without
errors

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-10 15:13:07 +00:00
..
acpi
arch smbios: Walk over PCI devicetree to fill type 9 2019-05-07 16:05:53 +00:00
commonlib vboot: include vb2_sha.h when required 2019-05-09 06:32:44 +00:00
console Fix code that would trip -Wtype-limits 2019-05-06 10:32:15 +00:00
cpu cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE 2019-04-25 15:56:28 +00:00
device device: ignore NONE devices behind bridge 2019-05-07 16:05:27 +00:00
drivers intel/fsp1_1: Drop remnants of pei_data 2019-05-07 15:59:10 +00:00
ec ec/lenovo/h8: Add VBOOT board support 2019-05-08 10:27:36 +00:00
include sconfig: Add SMBIOS type 9 entries 2019-05-07 16:04:56 +00:00
lib vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
mainboard mb/google/sarien: Move EC PTS/WAK function to mainboard 2019-05-09 00:25:44 +00:00
northbridge {src,util}: Remove duplicated includes 2019-05-07 16:15:56 +00:00
security vboot: include vb2_sha.h when required 2019-05-09 06:32:44 +00:00
soc soc/intel/braswell/smbus: Enable early SMBus in romstage 2019-05-10 15:13:07 +00:00
southbridge sb/i82801gx: Remove duplicated 'define PMBASE' 2019-05-10 15:12:29 +00:00
superio superio/fintek/f71808a: Add more optional ramstage registers 2019-05-01 00:09:57 +00:00
vendorcode vendorcode/google/chromeos: Use explicit zero check in ACPI code 2019-05-09 15:34:53 +00:00
Kconfig spd_bin: Do not depend CONFIG_DIMM_MAX on CONFIG_GENERIC_SPD_BIN 2019-05-06 10:31:38 +00:00