Saurabh Mishra 1057865a89 soc/intel: Add Panther Lake PCIE device IDs ... Add Panther Lake specific CPU and PCIE device IDs Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81849 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2024-05-14 13:11:04 +00:00
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cpu_ids.h	soc/intel: Add Panther Lake PCIE device IDs	2024-05-14 13:11:04 +00:00
em64t100_save_state.h
em64t101_save_state.h
fsb.h
l2_cache.h	src: Remove unnecessary semicolons from the end of macros	2023-11-10 15:27:45 +00:00
microcode.h
msr.h	arch/x86: Reduce max phys address size for Intel TME capable SoCs	2023-09-12 08:12:02 +00:00
post_codes.h	src/*/post_code.h: Change post code prefix to POSTCODE	2023-08-05 16:04:46 +00:00
smm_reloc.h
speedstep.h
turbo.h