Keno Fischer 1044ebaa06 soc/intel: Add some missing MCH PCIe IDs ... These are documented in the Intel Datasheet entitled "6th Generation Intel® Processor Datasheet for S-Platforms" "6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2) Without them, coreboot fails to properly inform the payload of the amount of available memory. Signed-off-by: Keno Fischer <keno@juliacomputing.com> Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2019-06-07 10:08:35 +00:00
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apollolake	src/soc/intel/common/smbios: Add addtional infos to dimm_info	2019-06-06 11:32:52 +00:00
baytrail	soc/intel/baytrail: set default VBIOS filename and PCI ID	2019-06-02 22:26:34 +00:00
braswell	soc/intel/braswell: Use common cpu/intel/car code	2019-06-04 11:25:32 +00:00
broadwell	src/soc/intel: Avoid NULL pointer dereference	2019-06-03 18:24:06 +00:00
cannonlake	src/soc/intel/common/smbios: Add addtional infos to dimm_info	2019-06-06 11:32:52 +00:00
common	soc/intel: Add some missing MCH PCIe IDs	2019-06-07 10:08:35 +00:00
denverton_ns	soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE	2019-05-29 20:24:13 +00:00
fsp_baytrail	soc/intel/fsp_baytrail/romstage: Remove variable set but not used	2019-05-23 08:58:33 +00:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de/romstage: Remove variable set but not used	2019-05-23 08:58:15 +00:00
icelake	src/soc/intel/common/smbios: Add addtional infos to dimm_info	2019-06-06 11:32:52 +00:00
quark	soc/intel/quark: Don't use CAR_GLOBAL	2019-05-29 20:05:06 +00:00
skylake	soc/intel: Add some missing MCH PCIe IDs	2019-06-07 10:08:35 +00:00
Kconfig	src/cpu: Remove dead sourced lines	2018-11-15 10:25:20 +00:00