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Naresh Solanki 0f973d6e61 soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree 
The board has three SATA controllers, so add the remaining two
on PCI device 18.0 and 19.0.

TEST=Verify in lspci the sata controllers.

Change-Id: Ia654c4ef895b52338554d89c25f61b262fbbcbbb
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77892
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-10-13 13:51:50 +00:00
..
amd soc/amd/genoa/include/data_fabric: add VGA decode enable register 2023-10-12 23:14:17 +00:00
cavium Kconfig: Bring HEAP_SIZE to a common, large value 2023-10-11 12:09:01 +00:00
example/min86 soc: Remove SOC_SPECIFIC_OPTIONS 2023-08-21 23:45:43 +00:00
intel soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree 2023-10-13 13:51:50 +00:00
mediatek memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
nvidia memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
qualcomm Kconfig: Bring HEAP_SIZE to a common, large value 2023-10-11 12:09:01 +00:00
rockchip memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
samsung memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
sifive/fu540 memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
ti
ucb/riscv