<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <console/uart.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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static void oxford_oxpcie_enable(struct device *dev)
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{
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printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
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struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
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if (!res) {
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printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
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return;
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}
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void *bar0 = res2mmio(res, 0, 0);
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printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
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(read32(bar0) >> 8), (read32(bar0) & 0xff));
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printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
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(read32(bar0 + 4) & 3));
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printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
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}
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static void oxford_oxpcie_set_resources(struct device *dev)
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{
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pci_dev_set_resources(dev);
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/* Re-initialize OXPCIe base address after set_resources */
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u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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oxford_remap(mmio_base & ~0xf);
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}
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static struct device_operations oxford_oxpcie_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = oxford_oxpcie_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = oxford_oxpcie_enable,
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};
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static const struct pci_driver oxford_oxpcie_driver __pci_driver = {
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.ops = &oxford_oxpcie_ops,
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.vendor = 0x1415,
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.device = 0xc158,
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};
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static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = {
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.ops = &oxford_oxpcie_ops,
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.vendor = 0x1415,
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.device = 0xc11b,
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};
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